Exemplar Logic's Leonardo Spectrum software installed on jason.sdsu.edu is a versatile and interactive logic synthesis, optimization, and analysis tool developed to allow the use of technology-independent design methods for ASICs, FPGAs, and CPLDs. Designers can efficiently and economically consolidate multiple designs into one design, manipulate the design hierarchy, and use HDLs to accomplish their design. Leonardo's Timing Module adds sophisticated design verification, including constraint driven timing optimization, back-annotation, and VITAL simulation library support.

To run leonardo on jason.sdsu.edu, invoke the following command from a terminal window:

leonardo &

Documentation and User's Guides for Leonardo Spectrum

View Exemplar/ModelSim tutorial for CPLDs (PDF 294KB)

View an Introduction to VHDL Synthesis using Leonardo Spectrum (v1999.1j, PDF 1.4MB)

View the Leonardo Spectrum command reference manual (v1999.1j, PDF 1.0MB)

View the Leonardo Spectrum synthesis and technology guide (v1999.1j, PDF 3.0MB)

View the Leonardo Spectrum User's Guide (v1999.1j, PDF 3.7MB)

View the lGen User's Guide (v1999.1j, PDF 308KB)

View the Leonardo Spectrum Release Notes for version 1999.1j (v1999.1j, Text 63KB)

Please contact Christopher Paolini if you have any trouble using Leonardo Spectrum. Christopher Paolini's e-mail address is paolini@kahuna.sdsu.edu